Peking University, September 3, 2026: As the auto industry is accelerating toward AI-powered autonomous vehicles (AV), autonomous driving chips are emerging as a key determinant of whether safe, scalable, and commercially viable autonomy can be achieved. In a close examination of how chip design can address these requirements, a joint Peking-Tsinghua research team has proposed, in a Perspective, a cross-layer roadmap for next-generation intelligent chips. The Perspective, titled “Autonomous driving chips,” brought together 59 researchers from more than 20 institutions and was published in Nature Reviews Electrical Engineering.
Background
Autonomous driving places high demands on intelligent chips, with stringent requirements for multimodal perception, large-model inference, real-time decision-making, and safety. As AI models continue to grow in scale, increasing constraints on power consumption, heat dissipation, memory bandwidth, and reliability are widening the gap between algorithmic demands and available hardware capabilities.
Why it matters
The researchers argue that model scaling, advances in semiconductor manufacturing, or isolated architectural improvements alone will not be enough to support higher levels of autonomous intelligence. Instead, next-generation chips will require coordinated innovation across algorithms, computing architectures, semiconductor devices, advanced materials, and integration technologies.
This cross-layer approach shifts the focus from peak computing power alone toward improving a host of factors, including computing density, energy efficiency, real-time responsiveness, safety, and reliability. These capabilities are essential for autonomous systems that must make rapid and accurate decisions with limited energy and computing resources.
Key findings
The Perspective identifies hardware–software co-design as a central strategy for addressing the growing mismatch between increasingly complex AI models and limited on-board computing resources.
At the software level, model compression, efficient inference, and hardware-aware optimization can reduce demands on computing power, memory, and data transfer. At the hardware level, domain-specific architectures, in-memory computing, and cloud–edge collaboration can improve parallel processing and data utilization, helping to alleviate performance and energy bottlenecks associated with memory access and data movement.
The Perspective also highlights advanced logic and memory devices, chiplet technology, heterogeneous integration, and domain-specific architectures. These technologies could increase device density and shorten the data paths between computing and memory, improving both performance and energy efficiency.
Looking beyond conventional silicon technologies, the researchers examine emerging approaches such as carbon nanotubes, two-dimensional semiconductors, neuromorphic computing, and photonic computing. As traditional semiconductor devices approach their physical scaling limits, these technologies could provide new foundations for high-performance and energy-efficient computing in the post-Moore era.
Figure 1. Overview of autonomous vehicle systems.
Figure 2. Integrating artificial intelligence and hardware for scalable safe autonomous vehicles.
Future Implications
By connecting advances from algorithms to materials, the roadmap offers a systematic path toward safer, more efficient, and more reliable intelligent chips. Beyond autonomous vehicles, it could support embodied robots, low-altitude aircraft, industrial unmanned systems, disaster response, and space and deep-sea exploration.
*This article is featured in PKU News "Why It Matters" series.
More from this series.
Read more: https://www.nature.com/articles/s44287-026-00319-1
Written by: Akaash Babar
Edited by: Chen Shizhuo
Source: PKU News (
Chinese)
